Appendix A. Resource Utilization; Latticeecp2 And Latticeecp2S Fpgas; Ordering Part Number; Latticeecp2M And Latticeecp2Ms Fpgas - Lattice Semiconductor 10 Gb+ Ethernet MAC IP User Manual

This appendix gives resource utilization information for Lattice FPGAs using the 10 Gb+ Ethernet MAC IP core.
IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER
design tools. Details regarding the usage of IPexpress can be found in the IPexpress and Diamond or ispLEVER
help system. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at:
www.latticesemi.com/software.

LatticeECP2 and LatticeECP2S FPGAs

Table A-1. Performance and Resource Utilization
Mode
Multicast Address Filtering
1. Performance and utilization data are generated using an LFE2-35E-7F672C device with Lattice's Diamond 1.1 software with Synplify Pro
D-2010.03L-SP1 synthesis. Performance may vary when using a different software version or targeting a different device density or speed
grade within the LatticeECP2/S family.
2. The 10 Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O
Buffers integrated in the LatticeECP2 series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize
I/O pins.

Ordering Part Number

The Ordering Part Number (OPN) for the 10 Gb+ Ethernet MAC IP core targeting LatticeECP2 devices is 
ETHER-10G-P2-U4.

LatticeECP2M and LatticeECP2MS FPGAs

Table A-2. Performance and Resource Utilization
Mode
Multicast Address Filtering
1. Performance and utilization data are generated using an LFE2M35E-7F672C device with Lattice's Diamond 1.1 software with Synplify Pro
D-2010.03L-SP1 synthesis. Performance may vary when using a different software version or targeting a different device density or speed
grade within the LatticeECP2M/S family.
2. The 10 Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O
Buffers integrated in the LatticeECP2M series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize
I/O pins.
Ordering Part Number
The Ordering Part Number (OPN) for the 10 Gb+ Ethernet MAC IP core targeting LatticeECP2M devices is 
ETHER-10G-PM-U4.
IPUG39_02.9, December 2010
1
SLICEs LUTs
3153 4022
1
SLICEs LUTs
3153 4370
47
Resource Utilization
External
2
Registers Pins
2777 78
External
2
Registers Pins
2777 78
10 Gb+ Ethernet MAC IP Core User's Guide
Appendix A:
sysMEM™
EBRs f (MHz)
MAX
4 170
sysMEM
EBRs f (MHz)
MAX
4 180