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Lattice Semiconductor
Figure 2-2
shows a system block diagram for the 10 Gb+ Ethernet MAC IP core.
Figure 2-2. 10 Gb+ Ethernet MAC Core System Block Diagram
txmac_clk_ref
User
Application
Logic
FPGA Top
The 10 Gb+ Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The
main function of the 10 Gb+ Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE
standard are met while transmitting a frame of data over Ethernet. On the receive side, the Ethernet MAC extracts
the different components of a frame and transfers them to higher applications through a FIFO interface.
IPUG39_02.9, December 2010
PLL
reset_n
tx_paustim[15:0]
tx_pausreq
tx_is_paused
tx_data_avail
tx_read
tx_data[63:0]
tx_byten[2:0]
tx_eof
tx_force_err
tx_empty
tx_statvec[25:0]
tx_staten
Receive and
Transmit
MAC
rx_statvec[27:0]
rx_staten
ignore_pkt
rx_write
rx_data[63:0]
rx_byten[2:0]
rx_sof
rx_eof
rx_error
10Gb+ MAC IP Core
0
1
xgmii_tx_clk
ODDR
xgmii_rx_clk
PLL
txmac_clk
txd[63:0]
txc[7:0]
XGMII
rxmac_clk
rxd[63:0]
rxc[7:0]
mac_addr[47:0]
mode[1:0]
tx_cfg[3:0]
pause_opcode[15:0]
tx_ipg[4:0]
max_frm_len[13:0]
rx_cfg[6:0]
vlan_tag[15:0]
vlan_tag_en
tx_rx_status[4:0]
mc_table[63:0]
rdstat_raddr
trdstat_rdrqst
trdstat_rdack
trdstat_rdata[scw-1:0]
Statistics
Counters
rrdstat_rdrqst
rrdstat_rdack
rrdstat_rdata[scw-1:0]
7
10 Gb+ Ethernet MAC IP Core User's Guide
Functional Description
XGMII
IODDR
xgmii_txd[31:0]
xgmii_txc[3:0]
xgmii_rxd[31:0]
xgmii_rxc[3:0]
SM I
User
Register
HI
and
I/O
Processor
Buffers
Interface
Logic
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