Synthesizing And Implementing The Core In A Top-Level Design - Lattice Semiconductor 10 Gb+ Ethernet MAC IP User Manual

Lattice Semiconductor
The top-level file supporting ModelSim eval simulation is provided in 
\<project_dir>\ten_gbe_eval\<username>\sim\modelsim. This FPGA top is instantiated in an eval tes-
tbench provided in \<project_dir>\ten_gbe_eval\testbench\sc that configures FPGA test logic regis-
ters and 10 Gb+ Ethernet MAC IP core control and status registers via an included test file stimulus_file.v provided
in \<project_dir>\ten_gbe_eval\testbench\tests\sc. Note the user can edit the stimulus_file.v file to
configure and monitor whatever registers they desire.
Users may run the eval simulation by doing the following:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose folder
\<project_dir>\ten_gbe_eval\<username>\sim\modelsim.
3. Under the Tools tab, select Execute Macro and execute one of the ModelSim "do" scripts shown.
The top-level file supporting Aldec Active-HD
\<project_dir>\ten_gbe_eval\<username>\sim\aldec. This FPGA top is instantiated in an eval test-
bench provided in \<project_dir>\ten_gbe_eval\testbench\sc that configures FPGA test logic registers
and 10 Gb+ Ethernet MAC IP core control and status registers via an included test file stimulus_file.v provided in
\<project_dir>\ten_gbe_eval\testbench\tests\sc. Note the user can edit the stimulus_file.v file to
configure and monitor whatever registers they desire.
Users may run the eval simulation by doing the following:
1. Open Active-HDL.
2. Under the Console tab, change the directory to:
<project_dir>\ten_gbe_eval\<username>\sim\aldec ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
3. Execute the Active-HDL "do" scripts shown.
The simulation waveform results will be displayed in the Aldec Active-HDL Wave window.

Synthesizing and Implementing the Core in a Top-Level Design

The 10 Gb+ Ethernet MAC IP core itself is synthesized and is provided in NGO format when the core is generated.
Users may synthesize the core in their own top-level design by instantiating the core in their top level as described
previously and then synthesizing the entire design with either Synplify or Precision RTL Synthesis.
Two example RTL top-level configurations supporting 10 Gb+ Ethernet MAC core top-level synthesis and imple-
mentation are provided with the 10 Gb+ Ethernet MAC IP core in 
\<project_dir>\ten_gbemac_eval\<username>\impl.
The top-level file ten_gbemac_core_only_top.v provided in 
\<project_dir>\ten_gbemac_eval\<username>\src\rtl\top supports the ability to implement just the
10 Gb+ Ethernet MAC core. This design is intended only to provide an accurate indication of the device utilization
associated with the core itself and should not be used as an actual implementation example.
The top-level file ten_gbemac_reference_top.v provided in 
\<project_dir>\ten_gbemac_eval\<username>\src\rtl\top supports the ability to instantiate, simu-
late, map, place and route the Lattice 10 Gb+ Ethernet MAC IP core in a complete example design. This reference
design basically provides a loopback path for packets on the MAC Rx/Tx client interface, through a FIFO and asso-
ciated logic. Ethernet packets are sourced to the Rx XGMII and looped back on the MAC Rx/Tx Client FIFO inter-
face. Source and destination addresses in the Ethernet frame can be swapped so the looped back packets on the
Tx XGMII have the correct source and destination addresses. This is the same configuration that is used in the
evaluation simulation capability described previously. Note that implementation of the reference evaluation configu-
ration is targeted to a specific device and package type for each device family.
IPUG39_02.9, December 2010
simulation is provided in 
®
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IP Core Generation
10 Gb+ Ethernet MAC IP Core User's Guide