Lattice Semiconductor 10 Gb+ Ethernet MAC IP User Manual page 9

Lattice Semiconductor
The user can specify whether the FCS field should be written into the FIFO by programming the receive MAC con-
figuration register. If the FCS field is to be stripped off the frame, any padding bytes within the frame will be stripped
off as well.
Once a valid start of frame is detected, the destination address field of the incoming frame is analyzed. If the desti-
nation address was a unicast address, it is compared with the programmed MAC address. Unless the PRMS bit
was set in the RX_CTL register, the incoming frame will be discarded if the destination address field and the pro-
grammed MAC address do not match.
If the frame had a multicast address and if receive_all_mc signal is not asserted, all such frames are dropped
(except pause frames). If the frame had a multicast address and if receive_all_mc signal is asserted, the multicast
frames are subject to address filtering rules as described below.
For all frames with multicast address, the CRC of the destination address is computed and the mid six bits of the
least significant byte of the CRC is chosen as the address to a hash table. The MAC implements an eight row table
with eight bits in each row. The lower three bits of the selected CRC are used to select one of these eight rows and
the next three bits are used to select one of the bits in the selected table. The incoming multicast frame is accepted
if the bit selected from the hash table was set to one. It is discarded if the bit selected was zero.
If the incoming frame had a broadcast address it will be accepted if the either the prms or the receive_bc bit was
set. A broadcast frame is discarded if none of these signals are set.
A statistics vector that provides information about the incoming frame is generated when an incoming frame is
received and transferred to the FIFO. A vector is not generated for all those frames that are discarded (No address
match or frame length less than 64 bytes) or ignored (user asserts the ignore_pkt signal).
The vector is used to drive the management information block counters that keep track of all the happenings on the
line. The composition of the statistics vector is shown in
Table 2-1. Rx MAC Statistics Vector
The full condition of the FIFO can be avoided by asserting the ignore_pkt signal. At the time a new frame is
received, the receive logic samples this signal to determine whether the frame should be received.
Latency
Since the frame is buffered before being sent to the FIFO, there will be an initial latency. The first 64 bytes of a
frame are buffered before they are sent out. Since the internal data path is 64 bits wide, the latency from the time a
frame appears at the XGMII input to the time it begins to transfer to the FIFO will be eight clock cycles.
IPUG39_02.9, December 2010
Table 2-1.
Bit Description
25 Receive Packet Ignored
24 Minimum IPG Violated
23 Unsupported Opcode
21 Frame Too Long
20 In Range Length Error
19 PAUSE Frame
18 VLAN Tag Detected
17 CRC Error
16 Multicast Frame Received
15 Broadcast Frame Received
13:0 Frame Byte Count
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Functional Description
10 Gb+ Ethernet MAC IP Core User's Guide