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Other Functions - GE L90 Instruction Manual

L90 line current differential system ur series.
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2 PRODUCT DESCRIPTION
sors communicate their results to each other so that if any failures are detected, they can be reported to the user. Each
processor must successfully complete its self tests before the relay begins protection activities.
During both startup and normal operation, the CPU polls all plug-in modules and checks that every one answers the
poll. The CPU compares the module types that identify themselves to the relay order code stored in memory and
declares an alarm if a module is either non-responding or the wrong type for the specific slot. When running under nor-
mal power system conditions, the relay processors will have idle time. During this time, each processor performs back-
ground self-tests that are not disruptive to the foreground processing.
a) ALARMS
The relay contains a dedicated alarm relay, the critical failure alarm, housed in the power supply module. This output relay
is not user programmable. This relay has form-C contacts and is energized under normal operating conditions. The critical
failure alarm will become de-energized if the relay self test algorithms detect a failure that would prevent the relay from
properly protecting the transmission line.
b) LOCAL USER INTERFACE
The local user interface (on the faceplate) consists of a 2 × 20 liquid crystal display (LCD) and keypad. The keypad and dis-
play may be used to view data from the relay, to change settings in the relay, or to perform control actions. Also, the face-
plate provides LED indications of status and events.
c) TIME SYNCHRONIZATION
The relay includes a clock which can run freely from the internal oscillator or be synchronized from an external IRIG-B sig-
nal. With the external signal, all relays wired to the same synchronizing signal will be synchronized to within 0.1 millisecond.
d) FUNCTION DIAGRAMS
Sample Raw
Value
V
Sample Raw
Value
Sample
Hold
Remote Relay
GE Multilin
Offset
Removal
Charging Current
Offset
Comp.
Removal
dV
dt
Filter
PFLL Status
Phase and Frequency
Master
Locked Loop (PFLL)
Clock
PHASELETS TO REMOTE
Communications
Interface
Figure 2–3: L90 BLOCK DIAGRAM
L90 Line Current Differential System
Disturbance
Detector
Compute
Phaselets
67P&N
Compute
50P,N&G
Phaselets
UR Platform
51P,N&G
Phasors
Computations
27P
Compute
Phaselets
59P
21P&G
87L
Algorithm
Frequency
Deviation
Phase
Deviation
PHASELETS FROM REMOTE
Direct Transfer Trip
2.3 FUNCTIONALITY

2.3.3 OTHER FUNCTIONS

Trip Output
Configurable
Logic
831732A3.CDR
2-15
2

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