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UM2301
8.3
STWBC-EP layout
Figure 65: STWBC-EP digital controller layout
L501
1K
C501-L501 near
VDDA (pin13)
C501
100NF
22
DEMAGNET
23
SYMBOL_DETECT
C503-C502-L502
near VDD (pin29)
STWBC-EP
L502
1K
Digital controller
C502
100NF
R505
C503
31
1UF
10K
VOUT
27
SWIM
SWIM
28
RESET
NRST
21
DCDC_DRV
DCDC_DRV
24
DCDC_DAC
DCDC_DAC
DocID031141 Rev 1
Board assembly and layout
C103
C503
L502
C502
L501
C100
R505
C501
R505 near Reset
(pin 28)
C112
53/57
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