Interrupt Controller - Advanced Micro Computers Am96/4116A User Manual

CS*
RESET
RO*
PARALLEL CE* is used to enable the Am8255A during
parallel I/O operations.
RESET is 'Used duri ng POWER ON cycl e and at any
time the system is initialized.
10
READ* is used when either parallel data or
status bytes are read by the CPU.
WR*
10
WRITE* is used when either data or control
bytes are wY'itten by the CPU.
AO,Al ABI and AB2 allow selection by the CPU, of a
specific port or control word register.
Al
o
o
1
1
AO
o
1
o
1
SELECTION
Port A
Port B
Port C
Control Register
All internal registE~rs
are cleared and the ports are set to the high
impedance input mode when a high level is presented to the Reset input.
INTERRUPT CONT'ROLLER
The interrupt controller logic consists of an 8259A Interrupt
Controller and a jumper pad that allows the user to connect any of 32
possible interrupt requests to the 8259A eight interrupt priority
inputs.
The Interrupt Controller resolves priorities among the eight levels.
The priority resolution algorithm can be changed dynamically at any
time. This means that the complete interrupt structure can be modified
as required.
The operation of the Interrupt Controller is controlled via five
control lines and the data bus. The five control lines are decoded to
provide controls for programming and reading status. Control words and
status information are transferred through the data bus. The functions
of the control lines are as follows:
CS* RUPT CE* enabl es the 8259A control and status
operations.
C/O ABI is address bit
1.
Provides access to control
register When high and data when low.
RO*
10
REAO* permi ts readi ng of s'tatus i nformat i on by
the CPU.
4-9