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7
6
5
4
3
2
1
0 -
Bit No.
I I I I I I I I I
TxRDY
RxRDY
TxE
PE
Parity error
OE
Overrun error
FE
SYNDET
DSR
- - - - - - - - - - - - - - - - - -
Figure 3-6.
Am9551 Status Word Format
PARALLEL I/O INTERFACE PROGRAMMING
An Am825SA Programmable Peripheral Interface chips provide 24 parallel
signal
lines
for the transfer and control
of data to and
from
peripheral devices.
The chi p provides three 8 bit ports (A,
B,
and
C).
Each port can be
configured as either input or output, and port
~
on each chip is used
as control lines for ports A and
B
in some modes.
The operating modes
of the ports are controlled by outputting either an operation control
word or
,a
bit set/reset control word.
Table 3-2 is a configuration
guide for the Am8255A.
Am8255A ADDRESSING
There are four consecut i ve word addresses (FFE8H through FFEEH) for
contro 1, data transfer, and status read.
See table 3-1 for the port
addresses and their functions.
Am8255,A INITIALIZATION
The
Am82~)5A
is initialized by writing an operation control word to
addr'ess to define the mode and by writing a bit set/reset control word
for Port
C
control if required.
3-8
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