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RANDOM ACCESS MEMORY
The Am96/4116A has 3:2K bytes of dynamic RAM locatable in either upper
or lower 32K byte of the 64K address space.
The RAM cons i sts of
sixteen 16,384 x 1 dynamic devices with 200 nano-second access times.
Addressing of the devices consists of 7 bits of row address and 7 bits
of column address.
Buffer U76 is enabled for the row address, and U66
is enabl ed for the col umn address.
Accessi ng the RAMs requi res fi rst
1 atchi ng the row addr'ess, then the col umn address.
The Am96/4116A RAM
has a 11 of the row address st robes (RAS*) in common.
However, the
col umn address strobes
(CJ\S*)
are separate for each devi ce such that
the low and hi gh bytes can be enabl ed separately or for byte-writes
together for word operations.
Since the RAM dev i cles are dynami c, peri odi c refresh i ng is requi red.
Normal read/write operat i on refreshes the devi ces.
However, when the
RAM is not be'j ng accessed by the CPU, another refresh scheme must be
used.
The method used on the Am96/4116A is a separate row address
counter wh i ch
cyc 1
es through the
seVE~n
row addresses at a 77KHz rate or
one address every 13}.lS.
Dual binary counter U57 is the refresh address
counter.
During refresh cycles, the counter output drives row address
o
to 6 to refresh the RAM chipsQ
An algorithmic state machine
consisting of U62, U63, and U73 provides synchronization of refresh and
memory availability with both a
dE~layed
CPU clock and the 77 KHz
refresh clock.
ROM/EPROM
The on-board ROM consists of two devices of lK, 2K, or 4K byte capacity
each, for a maxi mum of 4K words or 8K bytes.
One ROM, U91 is for
odd-byte addresses (bi ts 0 to 7), and U75 is for even-byte addresses
(bits 8 to F).
Jumpers are provided for selection of ROM type.
Both
ROMs must be the
sam~
type.
Jumpers at the inputs to U71 are required
to
sE~l
ect ROM si ze.
The output of U71 is used to generate the EPROM
CE* signal.
Flip-flop U81 is used to enable or disable the shadow ROM
feature.
An I/O write to address FFFO disables the shadow ROM.
An I/O
write to address FFFI enables the shadow ROM address bi t
0
(ABO)
functions as the shadow ROM select line.
MEMORY EXPANSION
The memory expans i on feature of the Arn96/4116A uses the bi t set/ reset
capability of the parallel I/O Port C bits.
Connecting the required
jumpers (see figure
3-2),
and outputting the desired bits can select up
to 512K bytes of external ROM or RAM.
Buffer U92 is enabled only when
the on-board RAM space is not addressed.
If the on-board RAM is
located at 8000 to FFFF hex, the off-board bank sel ect address 1 i nes
are only valid in the address range from 0000 to 7FFF hex.
Using port
C bi tOto dri ve the ADF* (address bi t F hex), permi ts address i ng
32K-byte blocks.
However, the 321<-byte blocks are contiguous.
An
extra programming step of setting the port C bits is required, but up
to eight 64K RAM boards, for example, can be addressed.
4-5
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