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TABLE 1-1. SPECIFICATIONS (continued)
Shadow ROM
A Wr Ite canmand to I/O port FFFOH d I sab les
address Ing on-board Rav1 and causes ROM ad-
dresses
0
to 8K to
be
mapped to of f- board
RAM.
A Write to I/O port FFF1 enables on-
board RQ\1.
RAM Access
Type of Access:
2-port (Dual Access)
Walt States:
No wait states for access from Aml8002
Access Time from
1350-3275 nanoseconds
Multlbus, Command to
XACK Time:
w/2 port RAM lock:
First Access:
Subsequent Access:
1350-3275 ns
737-1087 ns
Multlbus Interface
Clocks:
BCLK and CCLK jumperable
Exchange Capability:
Serial priority on-board
Paral lei pr lorlty off-board
Bus Lock:
Wr Ite to I/O port FFF9H
locks the bus to
exclude other access. Write to I/O port FFF8H
un locks the bus.
Multibus Interrupts:
Non-bus vectored Interrupts are supported and
may
be
Implemented
with
the
following
options:
Interrupts
are
always
j
umpered.
recognized
when
J.L9
Port
Functions
Single Step Enable:
Bus vectored Interrupts are not supported.
FFCOH
1-6
Interrupt Contro I Ier
Data:
FFC8H
Control:
FFCAH
(Am8259A) :
Timer (Am9513):
Data:
FFDOH
Control:
FFD2H
Serl"al
I/O Port #1
Data:
FFD8H
Control ::
FFDAH
(Am9551 ):
Serial
I/O Port #2
Data:
FFEOH
Control:
FFE2H
(Am9551):'
----_
..
-
..
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