Master Mode Register; Time Of Day - Advanced Micro Computers Am96/4116A User Manual

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FOUl Divider - - - - - - -
0000
==
Divide by 16
0001
==
Divide by 1
0010
==
Divide by 2
0011
==
Divide by 3
0100
==
Divide by 4
0101
==
Divide by 5
0110
==
Divide by 6
0111
==
Divide by 7
1000
==
Divide by a
1001
==
Divide by 9
1010
==
Divide by 10
1011
==
Divide by 11
1100
==
Divide by 12
1101
=
Divide by 13
1110
=
Divide by 14
1111
=
Divide by 15
FOUl Glte
0== FOUT On
1 == FOUT Off (Low Z to GND)
Data Bu. Width
o
== a-Bit Bus
1 0= 16-Bit Bus
Data Pointer Control
o
==
Enable Increment
1
=~
Disable Increment
Seller Control
o
=
Binary Division
1 == BCD Division
FOUl Source
0000
==
F1
0001
==
SRC 1
0010
==
SRC 2
0011
==
SRC 3
0100
=
SRC 4
0101
==
SRC 5
0110
==
GATE 1
0111
=
GATE 2
1000
=
GATE 3
1001
==
GATE 4
1010
==
GATE 5
1011
=
F1
1100
==
F2
1101
==
F3
1110
==
F4
11'11
==
F5
compare. 2 Enable
~
J
o
==
Disabled
1
==
Enabled
Compare 1 Enable
o
==
Disabled
1
==
Enabled
lime·of~Day
Mode - - - -
00
==
TOO Disabled
01
=
TOO Enabled:
~
5 Input
10
==
TOO Enabled:
~
6 Input
11
==
TOO Enabled:
~
10 Input
' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
Figure 3-13.
Master Mode Register Bits
TIME OF DAY
Bits MMO and MM1 of the Master Mode register specify the time-of-day
(TOO) options.
When MMO
=
a
and MM1
=
0, the special logic used to
implement TOO is disabled and counters 1 and 2 will operate in exactly
the same ways as counters 3, 4, and
5.
When MMO
=
1 or MM1
=
1,
additional counter decoding and control logic is enabled for counters 1
and 2 whi ch causes them to turn-over at the counts that generate
appropriate 24-hour TOO accumulations.
Figure 3-14 shows the counter configurations for TOO operation.
The
two most significant decades of Counter 2 contain the hours digits and
they can hold a maximum count of 23 hours.
The two least significant
decades of Counter 2 i ndi cate mi nutes and wi
11
hol d va
1
ues up to
59.
The three most s i gni ficant decades of Counter 1 i ndi cate seconds and
will
contain values 'up to
59.9.
The least significant decade of
Counter 1 is used to scale the input frequency in order to output
3-20

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