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A circuit consisting of U37, U45, U26 and U84 provides power-on
initialization for the Am96/4116.
In addition, the INIT* pin (PI-14)
may be used as an external reset input to the Am96/ 4116.
A jumper
position is available to permit initialization of other boards in the
system as well.
The jumper should be installed between pins 190 and
191.
The AmZ8002 shares a 16-b it da tabu s with the address bus.
Two
signals, address strobe (AS*) and data strobe (OS*) are used to
multiplex the 16-bit bus..
Bus transceivers U69 and U79 provide data
bus bufferi ng.
The address
1
i nes are
1
atched by U68 and U78 by an
inverted AS* si gnal •
Bus transcei ver U94 and U86 provi de buffered
addresses to externa'l locations and access to the on-board dual-port
RAM.
When BUSAK* goes low, access to on-board RAM is ava i
1
ab
1
e.
At
the same time, the latches U68 and U78 are in a high-impedance mode.
The dual port RAM logic consists of a state machine U62, U63, and U73.
The state machine controls arbitration between the Multibus, CPU, and
refresh cycles.
Dual
port RAM control
logic consists of digital
comparator U85.
Jumpers are ava i
1
ab
1
e to determi ne the address an external processor
uses to access the Am96/4116
RA~1..
The output of U85 dri ves a
synchronizing flip-flop U81 to produce ZBUSRQ* to request the bus from
the AmZ8002.
The CPU will respond with ZBUSAK*.
Bus transceivers U87, U8B, and U95 provide data bus buffering between
the AmZ8002 and the off-board
d(~vi
ces
and memory.
Fi gure 4-2
illustrates word (16-bit) and (8-bit) byte operations.
NOTE
Even lines for the CPU are 08 to OF (bit 15), while
even on the Multibus pins are DO to 07.
Byte operat ions look onl
y
at data bi ts 0 to 7 (OATO-OAT7) of the
Multibus pins.
Odd-byte operations enable U87 and Even-byte operations
enable U88 (figure 4-2b and 4-2c).
Word operations enable both U8B and
U95 (fi gure 4-2a).
If the CPU shares an area of memory wi th an
external processor, only byte operati ons shoul d be used.
The AmZ8002
and the Mul t i bus ha
VE!
odd and even bytes reversed.
The I/O port decoding is performed by 3 to 8 line decoder U80.
Address
bits 3, 4, and 5 perform the I/O port selection.
Bits 14 and 15 (E and
F) determine the base address of COOO hex for the I/O area, which is
COOO to FFFF.
Status line decoding is performed by a fusible-link PROM
U51.
4-3
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