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Board Dimensions:
Width
Depth
Thickness
30.48 cm (12.00 inches)
17.15 cm ( 6.75 inches)
1.50 cm ( 0.60 inches)
Environmental Requirements:
Operating Temperature
O°C to 55°C
Relative Humidity
Up to 90% without condensation
Storage Temperature
-40°C to +75°C
FUNCTIONAL DESCRIPTION
The Arn96/4116A 'MonoBoard Computer contai ns an ArnZ8002 CPU, two Arn9551
serial ports, one Am8255A parallel I/O port, an Am9513 timer, an 8259A
interrupt cont ro
11
er, 32 k
il
ob.ytes of RAM, two sockets for 2K, 4K, or
8K of ROM, and various TTL circuits.
The board is compatible with the
Multibus interface requirements.
The ArnZ8002 CPU is an advanced
architecture,
16-bit microprocessor with an
instruction set more
powerful than many minicomputers.
There are sufficient resources, such
as sixteen 16-bit general purpose registers, seven data types, eight
addressing modes, and 110 distinct instruction types.
The 110 distinct
instructions can be combined with the various data types and addressing
modes to expand the instruction set to 414 instructions.
Most
instructions can use any of the five addressing modes and can operate
on byte (8-bit), word (16-bit), and long-word (32-bit) data, types.
Figure 1-1 is a block diagram of the Am96/4116A.
Selection of ROM is optional.
Two sockets are provided to accommodate
ROM"
The ROM type can be Arn2708 or Arn2758 (2 ki
1
obytes), Arn2716 or
Am9218 (4 kilobytes), or Arn2732 or Am9233 (8 kilobytes).
Jumpers are
provided to select the correct ROM addressing scheme to accommodate the
various ROMs.
Addresses for the Am2708 range from 0 through 07FFH; the
Am2716 addresses range from 0 through OFFFH; and the Arn2732 addresses
range from 0 through 1FFFH.
The ROM addressing range is 8,192 bytes.
If 2 kilobyte or 4 kilobyte
ROM is impl emented, the unused address space, from 0800 to 1FFFH or
1000 to 1FFFH, for 2 kilobyte or 4 kilobyte ROM, respectively, will be
mapped to off-board RAM.
A'll ROM on the Arn96/4116A MonoBoard Computer is Shadow ROM.
A Write
instruction addressed to port FFFOH disables on-board ROM and causes
memory access to addresses 0 through 1FFFH to be mapped to off-board.
Either ROM or RAM can be used as off-board memory; both read and write
operat ions at the off-board memory are allowed, even though a wri te
operation when ROM is used is meaningless.
A Write instruction
addressed to
port
FFF1H enables the on-board ROM.
When first
powered-up,
ROM is enabled.
Shadow ROM and RAM can occupy the same
1-2
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