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buffer to the transmi tter section.
In the synchronous mode, when the
proces sor does not load a ne\'1 byte into the buffer in time, TxE wi 11
momentaril y go to hi gh 1 eve 1 as SYNC characters are loaded into the
transmitter section.
TxE going high is independent of the status of
the TxEN bit in the command register.
Data Terminal Ready (DTR*)
This signal is a general purpose output
wh'lch reflects the state of bit 1 in the command instruction.
It is
commonly connected to an associated modem to indicate that the Am9551
is ready.
Data Set Ready (DSR*l This is a general purpose input signal and forms
part of the status byte that can be read by the processor.
The DSR*
si gnal is generally generated by the modem as a response to the DTR*
signal; it indicates that the modem is ready. The signal acts only as a
flag and does not control any internal logic.
Request to Send (RTS*)
Thi sis a general purpose output, simi 1 ar to
DTR*; it reflects the state of bit 5 in a command instruction.
RTS* is
normally used to initiate a data transmission by requesting the modem
to prepare to send.
Clear to Send
(CTS~
This is a general purpose input signal used to
enable the Am9551 to transmit data if the TxEN bit in the command byte
is a one.
CTS* is generally used as a response to RTS* by a modem to
indicate that transmission can begin.
Designers not using CTS* in
their systems should remember to tie it low so that
~n9551
data
transmission will not be disabled.
PARALLEL I/O INTERFACE
The Parallel I/O Interface on the Am96/4116A provides 24 lines for the
transfer and control of data to and from peripheral devices using one
Am8255A Programmable Peripheral Interface.
The Am8255A is organized as three 8-bit ports (A, B, and C).
Two of
the ports A and
B
have Am8304 bus transceivers installed, providing 16
bidirectional I/O lines.
As shipped from AMC, port A is configured as
an output port, and port
B
is configured as an input port.
Port C is
organi zed as two four-bit I/O ports, with sockets provi ded for either
1
i ne dri vers or termi nat ions (see fi gure 2-2 and table 2-8).
The
Am96/4116A has the capability of using port C bits
a
to 3 for block
selection of external memory.
Communication between the CPU and the Am8255A is via the data bus and
six control
lines.
Control
and data bytes are transmitted to a
Am8255A; status and data bytes are transmitted from a 8255A on the data
bus 0 to
7.
The six control lines provide the necessary conty'ol for all
Am8255A data bus
operat ions..
The fo 11 owi ng is a descri pt i on of the
con t ro 1 1 i nes :
4-8
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