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five-bit 5 field.
In a linear-select fashion, each bit in the 5 field
corresponds to one of the five general counters (51
=
Counter 1, 52
=
Counter 2, etc.).
When an 5 bit is a one, the specified operation is
performed on the counter so des i gnated; when an 5 bi tis a zero, no
operat i on occurs for the corresponqi ng counter.
Thi s type of command
format has three basic advantages:
•
Host software is conserved by allowing any combination of counters
to be acted on by a single command.
•
Facil i tates s
i
mul taneous act i on of mul t i pl e counters where syn-
chronization of commands is important.
•
Allows counter specific service routine to control
individual
counters regardless of the operating context of other counters.
STATUS REGISTER
The 8-bit read-only status regi ster i ndi cates the state of the Byte
Poi nter bit in the Data Poi nter regi ster and the state of the OUT
signal for each of the general counters shown in figure 3-12.
The OUT
signals reported are those internal to the chip just before the three
state interface buffer circuitry.
Thus, the status register reflects
the results of polarity control over the OUT signals, and continues to
indicate the counter condition even when the output is off.
SR7
SR6
SRS
SR4
SR3
SR2
SR1
SRO
1
1
OUT 4
OUT 2
BYTE
POINT
ER
L - -
,
_
OUT 5
OUT 3
OUT 1
Figure 3-12.
5tatus Register Bits
3-18
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