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The shadow technique essentially adds the PROM/ROM space to the direct
address size of the CPU, effectively increasing the usable address
space by up to
8K
bytes.
An I/O write to add ress FFFOH wi
11
di sab
1
e
the shadow ROM.
An I/O write to address FFFIH enables the shadow ROM.
When enabled, ROM space goes from
0000
to IFFFH, if
8K
of ROM is being
used.
Jumpers confi gure PROM/ROM space for IFFFH maxi mum.
If the
shadow ROM occupies the same physical memory space as RAM, the RAM can
be written to, but not read until shadow ROM is disabled.
This feature
permits copying all or part of ROM into RAM, and then using only RAM.
SERIAL I/O INTERFACE PROGRAMMING
Two Am9551 Programmable Communications Interface chips are used to
interface between the CPU data bus and two RS232C I/O ports.
One
Am9551 provides a full RS232C serial interface to P4. The other Am9551
provides a modified RS232C serial interface at P5. The modified serial
I/O port does not use the Data Set Ready and Clear To Send lines.
Programmable operating modes and, format options allow the Am9551 to
service a wide range of communications, disciplines, and applications.
Operating modes are determined by a mode instruction word and a command
instruction word.
Am9551 INITIALIZATION
The Am9551 chip is initialized as follows:
•
Reset the chi p by wri t ing a command word (wi th bit 6 set) to
hex address FFDAH or FFE2H.
•
LJri te a MODE i nst ruct i on word to command regi steY'.
NOTE
If the Am9551 is
1
ooki ng for a MODE when the reset
command word is written, multiple reset commands
must be issued.
•
If synchronous mode is selected, write one or two sync
characters as required.
•
Write a command instruction word to command register.
NOTE
After initialization, always check the status of the
TxRDY bi t pri or to wri ti ng data or
a
new command
word to the Am9551.
The TxRDY bit must be true to
prevent overwriting and subsequent loss of commands
or data. The TxRDY is inactive until initialization
has been completed.
3-4
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