Counter Logic Groups; Counter Load Register - Advanced Micro Computers Am96/4116A User Manual

performs a subsequent read of the Data Port, the data bus drivers are
enabled, outputting the pre-feteched data on the bus. Since the
i nterna
1
data regi ster is accessed pri or to the start of the read
operat ion, its access time is transparent to the user. In order to
keep the Prefetched data consistent with the Data Pointer, Prefetches
are a1so performed after each wri te to the Data Poi nter and after
execution at the Load Data Pointer command. The following rules should
be kept in mind regarding Data Port transfers:
• The data pointer register should always be reloaded before reading
from the Data Port if a command other than Load Data Pointer was
issued to the Am9513 following the last Data Port read or write.
The Data Po inter does not ha ve to be loaded aga in if the fi rst
Data Port transaction after a command entry is a write, since the
Data Port write will automatically causes a new prefetch to occur •
• Operating modes, N, 0, Q, and R allow the user to save the counter
contents in the Hol d
re~li
ster by applyi ng an act i ve-goi ng gate
edge. If the Data Pointer register had been pointing to the Hold
register in question, the prefetched value will not correspond to
the new value saved in the Hold register. To avoid reading an
incorrect value, a new Load Data Pointer command should be issued
before attempt i ng to read the sa ved data. A Data Port wri te (to
another register) will also initiate a prefetch; subsequent reads
will access the recently saved Hol d regi ster data. Many systems
wi
11
use the sa vi ng gate edge to interrupt the host CPU. In
systems such as this the interrupt service routine should issue a
Load Data Pointer command prior to reading the saved data.
COUNTER LOGIC GROUPS
Each of the fi ve Counter Logi c Groups cons i sts of a 16 -bi t genera
1
counter with associated control and output logic, a 16-bit Load
reg'i ster , a 16 -bi t Hold regi ster and a 16 -bi t Mode regi ster. In
add'ition, Counter Groups 1 and
2
also include 16-bit comparators and
16-bi tAl arm regi sters • The compa rato r / a
1
arm funct ions are cont ro
11
ed
by the Master Mode regi ster. The operat i on of the Counter r10de
reg; sters is the same for all fi ve counters. The host CPU has both
read and write access to all registers in the Counter Logic Groups. The
counter itself is never directly accessed.
COUNTER LOAD REGISTER
The read/write Load register is used to control the effective length of
the general counter. Any 16-bit value can be written into the Load
register. That value can then be transferred into the counter each time
the Termi na
1
Count (TC) occurs. Termi na
1
Count is defi ned as that
peri od of time when the counter contents woul d ha ve been zero if an
externa
1
va
1
ue had not been transferred into the counter. Thus, the
terminal count frequency can be the input frequency divided by the
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