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7 6 5
4
3
2
o
~
aitNo.
Sync mode
00
5 bits per character
01
6
bits per character
10
7 bits per character
11
8
bits per character
o =
Parity disable, 1
=
Parity enable
o
=
Odd parity, 1
=
Even parity
o
=
SYN DET output
1
=
SYN DET input
o
=
2 SYNC characters
1
=
1 SYNC character
'--------~----,---,--------------------------'
Figure 3-3. Am9551 Synchronous Mode Control Code
r - - - - - - - - - - - - ' - - - - -
7
6
5
4
3
2
o
~
Bit No.
Invalid
Async mode, 1 x Baud rate factor
Async mode, 16 x Baud rate factor
Async mode, 64 x Baud rate factor
' - - - - - - - - - - - - - - - - - -
00
5 bits per character
01
6 bits per character
10
7 bits per character
11
8 bits per character
o
=
Parity disable, 1
=
Parity enable
o
=
Odd parity, 1
=
Even parity
00
Invalid
01
1 stop bit
10
1 % stop bits
11
2 stop bits
Figure 3-4. Am9551 Asynchronous Mode Control Code
Am9551 STATUS READ
The CPU can determine the status of the Am9551 any time by issuing an
I/O input to addresses FFDAH and FFE2H.
The format of the status byte
is shown in figure 3-6.
The definition of the status bits is as follows:
3-6
TxRDY
Transmitter Ready indicates the Am9551 is ready to
accept a data character or command.
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