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tenth-of-second peri ods into the next decade.
It can be set up to
di vi de by fi ve (MMO :: 1, MM1
=
0), di vi de by six (MMO
=
0, MM1
=
1), or
di vi de by ten (MMO :: 1, MM1
=
1).
The input frequency, therefore, for
real-time clocking can be, respectively, 50Hz, 60Hz or 100Hz.
For the
Am96/4116, an input frequency of 2.4576 MHz must be divided by 40,960
and the TOO input di vi
dey'
set 60 Hz input.
Thi sis accompli shed by
selecting FOUT Source for F4, scaler control to binary and FOUT Divider
to di vi de-by-10.
The iMaster Mode Regi ster bits provi de the proper
configuration.
A
jumper (188 to 189) must be connected also.
NOTE
LJhen TOO oj s used, the seri a 1 Baud Rates cannot be
taken from FOUT (see paragraph 3-46).
COMPARATOR ENABLE
Bits MM2 and MM3 control the Comparators associated with Counters 1 and
2.
When a Comparator is enabled, its output is substituted for the
normal counter output on the assoc"jated OUT1 or OUT2 pi n.
Once the
compare output is true, it remains true until the count changes and the
compari son therefore' goes false.
The two Comparators can a 1 ways be
used individually in any operating mode.
One special case occurs when
the time-of-day opt;:onis selected and both Comparators are enabled.
The operation of Comparator 2 is then conditioned by Comparator 1 so
that a full 32-bi t compaY'e must be true in order to generate a true
signal on OUT2.
OUTI continues, as usual, to reflect the state of the
16-bit comparison between Alarm 1 and Counter 1.
C15
C12
C8
C4
co
Co, " "
2
0
]
Hours
Minutes
C15
C12
C8
C4
CO
co,,,e"LI
]
Seconds
1/10
Sec.
-;. 5,6, or 10
Figure 3-14.
Time-af-Day Configuration
3-21
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