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concatenated, it is possi b 1 e to confi gure a counter that is 80 bits
long on one Am9513 chi p.
When TCN-l is the source, the count ri ppl es
between the connected counters.
External connections can also be made,
and can use the toggl e bi t for even longer count s.
Thi sis eas i ly
accomplished by selecting a TOG output mode and wiring OUTN toone of
the SRC inputs.
GA TING CONTROL
Counter Mode bits
CM13 through CM15 specify the hardware gating
options.
When no gating is selected (000), the counter will proceed
unconditionally as long as it is armed.
For any other gating mode, the
count process is conditioned by the specified gating configuration.
For a code of 100 in this field, counting can proceed only when the pin
labeled GATEN associated with Counter N is at a logic high level.
When
it goes low" counting is simply suspended until Gate goes high again.
A code of 101 performs the same function with an opposite acti ve
po 1 ari ty • Code sOlO and all offer' the same funct ions as 100, but
specify alternate input pins as Gating Sources.
This allows any of
three interface pi ns to be used as gates for a gi ven counter.
On
Counter 4, for example, pin 34, pin 35 or pin 36 can be used to perform
the
gating
function.
This
also
allows
a
single
Gate
pin
to
simultaneously control up to three counters.
For codes of 110 or' 111 in this field, counting proceeds after the
specified active Gate edge until one or two TC events occur.
~Jithin
thi s interval the Gate input is ignored, except for the retri ggeri ng
option.
When repet"ition is selected, a cycle is repeated as soon as
another Gate edge occurs.
Thi s mode is useful when i mpl ement i ng a
digital single-shot since the gate can serve as a convenient firing
trigger.
A 001 code in this field selects the TC output from the adjacent
lower-numbered
counter
as
the
gate.
Thus,
one
counter
can
be
configured to generate a counting window for another counter.
ALARM REGISTERS AND COMPARATORS
Added functions are available in the Counter Logic Groups for counters
1 and
2.
Each contains a 16-bit Alarm register and a 16-bit
Comparator.
When the va 1 ue in the counter reaches the va 1 ue in the
A 1 arm regi ster, the Comparator output wi 11 go true.
The Master Mode
register contains control
bits to
individually enable/disable the
comparators. When en.abled, the comparator output appears on the OUT pin
of the associated counter in place of the normal counter output.
The
output wi 11 rema in true as long as the compari son is true, that is,
until the next input causes the count to change.
3-31
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