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TABLE 2-12.
SYSTEM BUS CONNECTOR PI PIN ASSIGNMENTS
(Circuit Side)
Pin
Mnemon Ic Descr I pt Ion
2 GND
S Igla I GND
4 +5
+5 VDC
6 +5
+5 VDC
8 +12
+12 VDC
10 -5
Not Used
12 -GND
Signal GND
14
INIT*
In It Iall ze
16 BPRO*
Bus Priority Out
18 BREQ*
Bus Request
20 MWTC*
Mem Write Command
22
10WC*
I/O Wr Ita Canmand
24
INH1*
Inhibit 1 CRAM)
26
INH2*
Not Used CROM)
28
ADR10*
See table 2-1
30 ADR 11*
see tab Ie 2-1
32
ADR12*
see table 2-1
34 ADR13*
see tab Ie 2-1
36
INT7*
38
INT5*
Interrupt Requests
40
INT3*
42
INT1*
44
ADRF*
46 ADRD*
48
ADRB*
50 ADR9*
Address Bus
52
ADR7*
54
ADR5*
56
ADR3*
58 ADR1*
60
DATF*
62
DATD*
64
DATB*
66
DAT9*
68
DAT7*
70
DAT5*
Data Bus
72
DAT3*
74
DAT1*
76
GND
S I gla I GND
78
Reserved
80
-12
-12 VDC
82
+5
+5 VDC
84
+5
+5 VDC
86 GND
Signal GND
ga
t
edge
(Canponent Side)
Pin
Mnemon Ic
Descr I pt Ion
1 GND
S Igla I GND
3 +5
+5 VDC
Power
5 +5
+5 VDC
Supp lies
7 +12
+12 VDC
9 -5
Not Used
11
GND
Signal GND
- -
13 BCLK*
Bus Clock
15 BPRN*
Bus Priority In
17
BUSY*
Bus Busy
19 MRDC*
Mem Read Canmand
Bus
21
ICRC*
I/O Read Command
Controls
23
XACK*
XFER Acknow Iedge
25 AACK*
Ad vanced Ackn ow Ied
27
BHEN*
Byte
HI~
Enable
29 CBRQ*
Canmon Bus Reques
31
CCLK*
Constant Clock
33
INTA*
Interr'upt Ackn ow I
- -
35
INT6*
InterrulPts
37
INT4*
Interrupt Requests
39
INT2*
41
INTO*
43
ACRE*
45 ADRC*
47
ADRA*
Addresses
49 ADR8*
Address Bus
51
ADR6*
53 ADR4*
55
ADR2*
57 ADRO*
59 DATE*
61
DATC*
63
DATA*
Data
65
DAT8*
67 DAT6*
69
DAT4*
71
DAT2*
Data Bus
73
DATO*
75
GND
S If1Ia I GND
77
---
Reserved
Power
79
-12
-12 VDC
Supp II es
81
+5
+5 VDC
83
+5
+5 VDC
85 GND
Signal GND
2-11
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