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value in the Load ll"egister.
In all operating modes, either Load or
Hold will be transferred into the counter when TC occurs.
In cases
where va 1 ues are bei ng accumul ated in the counter, the Load regi ster
action can become transparent by filling the Load register with all
zeros.
COUNTER HOLD R:EGISTER
The 16-bit read/write Hold register is dual-purpose.
It can be used in
the same way as the Load regi ster, thus offeri ng an alternate source
for modulo defi ni t i on for the counter.
The Hold regi ster can also be
used to store accumulated counter values for later transfer to the host
processor.
This a"llows the count to be sampled while the counting
process
proceeds
~1thout
interruption.
Transfer
of
the
counter
contents
into
the
Hold
register
is
accomplished
by
the
hardware
interface in some operati ng modes or' by software commands at any time.
COUNTER MODE
F~EGISTER
Each Counter Logic Group includes a Counter Mode (CM) register used to
control
all of the individual options available with its associated
general counter,.
These options include output configuration, count
control, count source and gating control.
Figure 3-17 shows the bit
assignments for the Counter Mode
rE~gisters.
The following paragraphs
describe the control
options in detail.
Note that generally each
counter is independently configured and does not depend on information
outside its Counter Logic Group.
The counter mode register should be
loaded only when the counter is disarmed.
After power-on reset or a Master Reset command, the Counter Mode
registers are initialized to a preset condition.
The value entered is
OBOO hex and results in the following control configuration:
Output low impedance to ground
Count down
Count bi na ry
Count once
Load register selected
No retri ggeri
n~l
F1 input source selected
Positive-true input polarity
No gating
3-27
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