Allen-Bradley MicroLogix 1400 Instruction Manual page 129

Programmable controllers
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Affect of HSC Output Mask on Base Unit Outputs
Output Address
HSC:0.HPO (high preset output)
HSC:0.OMB (output mask)
to the overflow value and the counter then begins counting from the
overflow value (counts are not lost in this transition). The user can specify
any value for the underflow position, provided it is less than the overflow
value and falls between -2,147,483,648 and 2,147,483,647.
To load data into the underflow variable, the control program must toggle
(low to high) the Set Parameters (HSC:0.0/SP) control bit. When the SP bit
is toggled high, the data currently stored in the HSC function file is
transferred/loaded into the HSC sub-system.
Data loaded into the underflow variable must be less than or equal to the
TIP
data resident in the low preset (HSC:0.LOP) or an HSC error is generated.
Output Mask Bits (OMB)
Description
Address
OMB - Output Mask Bits HSC:0.OMB
The OMB (Output Mask Bits) define which outputs on the controller can
be directly controlled by the high-speed counter. The HSC sub-system has
the ability to directly (without control program interaction) turn outputs
ON or OFF based on the HSC accumulator reaching the High or Low
presets. The bit pattern stored in the OMB variable defines which outputs
are controlled by the HSC and which outputs are not controlled by the
HSC.
The bit pattern of the OMB variable directly corresponds to the output
bits on the controller. Bits that are set (1) are enabled and can be turned
on or off by the HSC sub-system. Bits that are clear (0) cannot be turned
on or off by the HSC sub-system. The mask bit pattern can be configured
only during initial setup.
This table illustrates this relationship:
16-Bit Signed Integer Data Word
15 14 13 12 11 10 9
Using the High-Speed Counter and Programmable Limit Switch
Data Format
Type
word (16-bit binary) control read only
8
7
6
0
0
1
1
0
0
0
1
1
0
0
0
Publication 1766-RM001A-EN-P - October 2008
127
User Program Access
5
4
3
2
1
0
0
1
1
0
0
1
1
1
0
0
1
1

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