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efesotomasyon.com - Allen Bradley,Rockwell,plc,servo,drive
Using the High-Speed Counter and Programmable Limit Switch
113
This bit is transitional and is set by the HSC sub-system. It is up to the
control program to utilize, track if necessary, and clear (0) the overflow
condition.
Overflow conditions do not generate a controller fault.
Publication 1766-RM001A-EN-P - October 2008
- Quick Links:
- I/O Addressing
- Identifying Controller Faults
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