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Figure 2-175
Logic diagram of the overvoltage protection for the negative sequence voltage system U
The overvoltage protection for the negative sequence system can also be blocked via a binary input „>U2>(>)
BLK". The stages of the negative sequence voltage protection are automatically blocked as soon as an asym-
metrical voltage failure was detected („Fuse Failure Monitor", also see Section 2.24.1, margin heading „Fast
Fuse Failure Monitor (Non-symmetrical Voltages))" or when tripping of the MCB for voltage transformers has
been signalled via the binary input „>FAIL:Feeder VT".
During the single-pole dead time, the stages of the negative-sequence overvoltage protection are automatically
blocked since the occurring negative sequence values are only influenced by the asymmetrical power flow, not
by the fault in the system. If the device cooperates with an external automatic reclosure function, or if a single-
pole tripping can be triggered by a different protection system (working in parallel), the overvoltage protection
for the negative sequence system must be blocked via a binary input during single-pole tripping.
Overvoltage zero-sequence system 3U
Figure 2-176 depicts the logic diagram of the zero-sequence voltage stage. The fundamental component is nu-
merically filtered from the measuring voltage so that the harmonics or transient voltage peaks remain largely
eliminated.
The triple zero-sequence voltage 3·U
dress 3724). Combined with the associated time delays T 3U0> (address 3723) and T 3U0>> (address
3725), these stages form a two-stage overvoltage protection for the zero-sequence system. Here too, the drop-
out to pickup ratio can be set (3U0>(>) RESET, address 3729). Furthermore, a restraint delay can be config-
ured which is implemented by repeated measuring (approx. 3 periods).
SIPROTEC, 7SD5, Manual
C53000-G1176-C169-5, Release date 02.2011
0
is fed to the two threshold stages 3U0> (address 3722) and 3U0>> (ad-
0
2.19 Undervoltage and Overvoltage Protection (optional)
Functions
2
365
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