Main Cpu (Z80) - Epson PX-8 Technical Manual

REV.-A
7.1 Main CPU
(ZaO)
The main CPU is a CMOS-based, 8-bit microprocessor that controls the whole system. It directly
controls DRAM, the RS-232C interface and the expansion interface (CN8), and sends and received
commands and data both to and-from sub-CPUs 7508 and 6303 through the gate arrays.
Part No. X400260000 is currently used for the main CPU; however, jumper J 1 has been incorper-
ared on the MAPLE board so that in the future, other CPUs, which will expand the systems capabi-
lities, can also be used.
7.1.1 Operation
The main CPU operates at a clock rate of 2.45 MHz, making the instruction cycle approximately
1.6,us.
1 state
1 cycle
1/(2.45 x 10
8 )
= 408,us
408 x 4(4 states) = Approx. 1.6,us
Fig. 7-1 shows a block diagram of the main CPU. Registers consist of general-purpose registers,
accumulator registers, and flag registers.
Block diagram
Accumulator and Flag Registers
--.r----v- INSTRUCTION
DECODE
13
CPU AND
SYSTEM
CONTROL
SIGNALS
&
CPU
CONTROL
INST
REG
CPU
CONTROL
iii
-5V GND,p
7.1.2 Functions of Major Registers
1. Program counter (PC): 16 bits
Holds address of next instruction.
2. Stack pointer (SP): 16 bits
r - - -....
Interrupt Vector
Index Register IX
AlU
Index Register IY
Stack Pointer SP
,--_...I Program Counter PC
Fig. 7-1
Holds address of the top of the stack memory in DRAM.
3. Index register (IX and IV): 16 bits
Used for index addressing.
4. Memory refresh register (R): 8 bits
Memory Refresh R
Holds refresh address of DRAM. Lower seven bits are automatically incremented on execution
of op code fetch cycle.
5. Interrupt page address register
(I):
8 bits
Holds high-order 8 bits of the indirect address used for interrupt mode 2.
7-1