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REV.-A
Pin No.
Signal Name
In/Out
Function
-
40
RF
Out
Refresh signal for DRAM
41
DRA4
Out
DRAM address 4 (12)
42
DRA5
Out
DRAM address 5 (13)
43
DRA6
Out
DRAM address 6 (14)
- -
44
CAS1
Out
Column address strobe: CAS signal to DRAM
- -
45
S-INT
In
Interrupt signal from gate array GAH40M.
- -
Generates Z-INT signal and causes an inter-
rupt to main CPU.
46
BANK 1/0
In
Bank 0: Bank select signal from gate array
GAH40M. Bank 0 at low level and IPL ROM is
- -
selected at AB 1 5.
47
G
-
Ground
48
4.9 M
Out
Clock output gained by dividing 9.8 MHz
clock. Supplied to SED1320.
49
9.8 M
In
Clock input of 9.8404 MHz
50
2.45 M
Out
Clock output by dividing 9.8 MHz clock into
four. Clock for main CPU.
51
1 KC
Out
Clock output by dividing 32 KHz clock to 32.
Clock for sub-CPU 7508.
52
TEST
In
Test terminal. Normally kept low.
53
OFF
In
Initializes signal for the whole internal cir-
cuit. At high level, initializes all FFs. Hold 4.9
-
- -
M, 2.45 M, CS ROM, RD and Z-INT at high le-
- -
vel and others inactive. Outputs RSO.
54
32K
In
Basic clock input of 32.768 KHz. Generates 1
KC (Clock).
55
DW
In
Data write signal. W1 (write enable) control
data supplied from sub-CPU 7508 when
main CPU is on standby.
56
DCAS
In
Data CAS. CAS 1 control data supplied from
sub-CPU 7508 when main CPU is standby.
57
N/C
-
Not used
58
N/C
-
Not used
7-15
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