Epson PX-8 Technical Manual page 42

REV.-A
The voltage supplied to the voltage divider circuit may be considered to be the same as the VB
voltage. The current flowing through 032 is so small that the voltage drop across the transis-
tor is negligible. Thus, the divided voltage fed to the AD converter can be represented by the
following expression:
VB(V)· R5 7 VB·1 0000
VOUT
= R6g + R57 = 27800
The analog output (divider output) voltage equivalent to the digital value of D9H is given by mul-
tiplying the voltage represented by the least significant bit (SLB) (32 mY) by 217 (D9H). D9H is
equivalent to a voltage of approximately 1.7V at the input terminal AN1, as shown below.
E
=
~
x 21 7 ::; 1 .695 (V)
where 256 voltage represented by LSB.
The VB voltage which causes the divided voltage to be detected to be a low voltage is approxi-
mately 4.7V as given by the following expression:
(R69
+
R57) 2 .
VB(x) = R57 x 250 x 217 ....... ::; 4.71 (V)
Note: The above expressions do not take into account any errors such as the divider resistance
errors, etc., and they actually include a total error factor of ± 0.1 V.
The above low voltage detection is performed regardless of whether power is on or off. After
the after low voltage is detected, port 23 of the sub-CPU (pin 5) is back low to prevent further
battery power consumption. While power is off, the voltage is monitored every
10
seconds.
2.2.3.2 Voltage Sampling During Power Off
1. 12D, pin 11
1 D power supply control
2. 1 D, pin 5
SO (Serial Output)
3. 2E, pin 3
1 D CS control
5V 5V
1mS
G --------------------~----
G
--~I ~[II[ [[~III[
----lo..ooIE:=_
:
-----,~~II I ~
i j
I I ~
5V
Fig. 2-12
The output at pin 11 of the IC 12D is controlled at port 23 of the 7508 (2E) sub-CPU. While
power is off, it is held low for 8 ms every 10 seconds to power the IC .uPD7001 (1 D). Approxi-
mately 4 ms after the power supply to the IC, the CS signal is input to it for channel selection.
Once a channel is selected, the digital data of that channel is output to 1 D, pin 5.
2-18