Epson PX-8 Technical Manual page 57

REV.-A
(Serial Data/Command Transfer)
Data such as A-D conversion data which are exchanged between the following components are
serially transferred:
(1) Between sub-CPU 7508 (2E) and A-D converter 7001 (1 D)
• ANO channel selection and temperature data transfer
• AN 1 channel selection and battery voltage data transfer
• AN2 channel selection and external analog input data transfer
• AN3 channel selection and barcode data transfer
(2) Between sub-CPU 7508 (2E) and gate array GAH40M (4C)
• Channel selections listed in (1) above and data transfer
• Keyboard and DIP switch data transfer
Fig. 2-29 shows the transfer paths of the above serial data.
GAH40M
A A
Main CPU
{8-bit paralle;\
SCK
~
Z-80
1\
transfer
j
SI
-
(4A)
1
r
SO
SI: SERIAL IN
SO: SERIAL OUT
SC S K: HIFT C
LOCK
Fig. 2-29 Serial Data Transfer
SCK
SO
SI
SO
SI
SCK
7508
(2E)
7001
(1 D)
",1.
'--y----J
Analog channels
The operations listed in (1) and (2) above are controlled by the appropriate commands of the main
CPU and the sub-CPU 7508. The operation sequence executed when the main CPU reads data
from the A-D converter 7001 is shown below.
(1) Main CPU reads I/O address 05 and examines whether bit is on (high) - examines whether a
analog data read command may be issued by checking the state of the handshaking FF in the
gate array GAH40M (bit 0 of I/O address 05). If the previous command has been processed,
bit 0 is on, indicating that the command may be issued (as signalled by RDY SIO).
(2) Main CPU writes the 1-byte command at I/O address 06 (SIOR resistor) - stores the command
in the SIOR register in the gate array GAH40M.
(3) Main CPU writes bit 1 of I/O address "01" - this causes an interrupt to sub-CPU which informs
it that the command has been stored in the SIOR register (RDY SIO is reset).
(4) Sub-CPU issues eight shift clock (SCK) pulses to gate array and reads in the 8-bit command
from the SIOR register.
(5) According to the received command, sub-CPU activates (lowers) the CS signal to the A-D con-
verter to select it and then issues the channel selection data in synchronization with the shift
clock.
2-33