Epson PX-8 Technical Manual page 62

REV.-A
2.3.2.2 Memory Bank Switching
The main CPU controls memory using 1 6 address lines, making it capable accessing a memory
space of 64k bytes from address 0000 to FFFF. However, the CPU memory space includes a 32k
byte ROM and an option unit ROM, in addition to the 64k byte dynamic RAM. To allow the CPU to
access this entire memory space which is greater than 64k bytes, bank switching signals are
used.
Note: When a RAM disk is used as option unit, no memory back switching is made but the main
CPU controls the external RAM as an I/O port.
r---------
; Option unit
Address bus
I
\/
\1
il \
0
liank 0
GAH40D
~K2
GAH40M
32KB 64KB
OPTION
Main CPU
IPLROM D-RAM
ROM
j
I
I
+
,
I
~
I
~
Data bus
I
L _ _ _ _ _ _ _ _ _ _
Fig. 2-33 Memory Configuration
The entire memory space is divided into the four banks (listed in Table 2.5), which are se-
lected by a combination of the BANK 0 and BK 2 signals shown in Fig. 2-32.
Table 2-5 Memory Bank Selection
~
1 1 0 0
S-<l~
:to
0 1 0
1
Address
FFFF
D-RAM D-RAM
OPTION OPTION
)
(H) (H) ROM (H) ROM (H)
8000
7FFF
IPL ROM D-RAM IPL ROM
OPTION
)
(L)
ROM (L)
0000
As shown in Fig. 2-33, two band control signals, BANK 0 and BK 2, are used, both are fed to the
gate array GAH40D. Because BK 2 is pulled up on the MAPLE board, only the left two D-RAMs
and IPL ROM are addressed when no option unit (with ROM) is available.
2-38