Epson PX-8 Technical Manual page 160

\
REV.-A
Circuit Operations
The read signal from the read winding is fed to pin 6 of IC3, after its dc component is removed by
capacitor C13. Divided voltage from VLRO is supplied to pin 5 by the voltage divider circuit.
[
5
·47K
Vx= 33K+33K+47K
~
=2.0V
R33 R15
R17
47K
VX
VLSW
33K
33K
IC3, pins 5, 3
{ IC4, pin 3
R20
Pins 5 through 7 of IC3 form a negative feedback amplifier (G = - R14 ).
]
Pins
The output signal is fed, after its dc component is rejected by capacitor C18, to the next stage,
which is also a negative feedback amplifier
(G
= -
=~~
) .
The output of this amplifier is fed to the next filter circuit. It is also supplied to the speaker circuit
on the MAPLE board. Since no phase compensation is provided in the previous stages, the signal
here has some delay.
In the filter circuit, a high frequency component is removed by the T-type filter consisting of R26,
R27, and C23, and the amplifier circuit. The amplifier frequency response is varied to lower the
gain in a high frequency range.
The amplifier, consisting of pins 1 through 3 of IC3, detects signal peaks.
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Fig. 3.20 Read Circuit
3-14
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