Serial Controller 82C51 - Epson PX-8 Technical Manual

REV.-A
r-
7.8 Serial Controller 82C51
The 82C51 controls serial data transfers between the RS-232C interface and the option
unit. Its operation modes vary speed of tronsfer, parity, and character length, etc., modes are con-
trolled by a control word which is written in the 82C51 by the main CPU. Data are transferred one
byte at a time. The transmit and receive clock signals are supplied from the gate array GAH40M.
Figure 7 -17 is a block diagram illustrating 82C51 signal flow to and from external connectors.
Data bus
(GAH40D) RESET
(2.45 MHz) ClK
(ABO)
C/O
rRD
(GAH40M)
~WR
lcs
[DSR
(RS-232C)
~
DTR
CTS
lRTS
A
<
. .
,
,--------------,
lA
A
...
l-byte transmit
1
Data bus
buffer (with a
,0"
buffer
. .
...
paralle'to
I
serial conversion
I
feature)
I
I I~
I
I
\
I
I' A
. .
Read/write
Transmit
,
I '
control
..
0"
control
I
I '
...
circuit
,
I
,
..
I
I
l' r--
1-byte receive -
,
""-
buffer (with a
I
I
serial to paral-
I
...
lei conversion
~
feature
I'
~
i
I
I ..
MODEM
A
I
"
control
...
~
I
I
Receive ,
control
I
I
L ______________
~
Fig. 7-17 82C51 Serial Controller Block Diagram
L;.
...
...
,
L
....
TXD (RS-232C)
TXD Option
TXRDY}
TXE Not used
TXC (GAH40M)
RXD (RS-232C)
RXD (Option)
RXRDY}
RXC
SYNDET/BD (Not used)
The signals to the RS-232C interface are converted to the
±
8V (RS-232C) levels between 82C51
and the interface. The Carrier Detect (CD) signal, which is not included in the above block dia-
gram, is connected to the interrupt port of GAH40M to interrupt the main CPU.
The 82C51 itself can support both synchronous mode (BI-SYNC) and asynchronous mode (Start-
Stop system: includes start/stop bits); however, in this CPU, TXE and SYNDET/BD are not con-
nected for SYNC character control signals.
When an asynchronous system is used, processing on the SYNC character, etc. needs to be sup-
ported by the application software.
The 82C51 cannot simultaneously process transmit/receive data to and from the RS-232C inter-
face and option unit. Thus, the GAH40M AUX signal is provided to allow an external control for
enabling and disabling the RS-232C transmit/receive lines.
7-36