Epson PX-8 Technical Manual page 110

REV.-A
2.9.1.1 A-D Conversion
Turning the CS signal high causes the A-D conversion, using the selected analog input channel
when the sequence controller sets virtual bits to the sequential comparison register. An analog
voltage equivalent to the value of the bits set in the sequential comparison register is generated
by the converter and compared with the input analog voltage by a built-in comparator. It is then
determined whether or not to reset any of the virtual bits, depending on the compared result. This
operation is repeated until the exact combination of bits, which is equivalent to the input analog
voltage, is finally set in the sequential comparison register. This sequence of operations requires a
minimum of 56 clock pulses, and the entire sequence is repeated until the CS signal is turned low.
Thus, the sequential comparison register is refreshed approximately 14 every
11S
(2.5
Jis
x 56
=
140
Jis)
because the clock cycle is approximately 400 kHz.
2.9.1.2 Converted Digital Data Read
Turning the CS low causes the sequence controller to stop operating, terminating the conversion.
Approximately 12.5
Jis
(a duration of 5 clock pulses) after this, the internal CS signal, which is
used in the sequence controller, goes low, allowing the converter to be interfaced with the exter-
nal circuit via signal terminals such as SO and SCK, etc. The contents of the sequential compari-
son register have been set to the shift register by this time. Thus, when the shift clock (SCK) pulse
is supplied, the digital data is output over the SO line one bit at a time at the rising edge of the
pulse.
2.9.1.3 Output Data
A specific value of total error is inherent to this A-D converter due to its physical property which
varies depending on reference voltage. It internally converts an input analog voltage to a digital
value of eight bits. However, the total error at a reference voltage of 2.0V is equivalent to the two
least significant bits. Thus, only the six most significant bits are effective.
2.9.1.4 Timing
Fig. 2-89 shows a conceptual basic operation timing of the converter. The minimum conversion
time corresponds to a duration of 56 clock pulses, writch is approximately 140
Jis
(2.5
JiS
x 56
=
140
Jis)
because the clock cycle is approximately 400 kHz. Thus, a total data transfer time of ap-
proximately 400
JiS
is required for channel selection and digital data read.
2-86