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REV.-A
82CS1
1. Location: MAPLE Board, 13E
This is a serial
interface, CPU-programmable, USART chip which can
provide full-
duplex communications.
3. Pin Assignments
Oz
03
RXO
GNO
Dot
05
06
07
TXC
WR
CS
c/o
RO
RXROY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
~
01
Do
Vee
RXC
OTR
RTS
OSR
RESET
ClK
TxO
Tx EMPTY
CTS
SYNOET /80
Tx RO
Table 7-12 82CS1 Pin Assignments
Pin No.
Signal Name
Signal direction
Meaning
1
D2
In/Out
Data bus 2
2
D3
In/Out
Data bus 3
3
RXD
In
Receive data (from RS-232C interface or op-
tionl unit)
4
GND
-
Circuit ground
5
D4
In/Out
Data bus 4
6
D5
In/Out
Data bus 5
7
D6
In/Out
Data bus 6
8
D7
In/Out
Data bus 7
- -
9
TXC
In/Out
Data bus 7
-
10
WR
In
Transmitter clock
-
11
CS
In
Chip select
-
12
CD
In
Command/data
-
13
RD
In
Read signal (from 82C51 to data bus)
7-37
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