Epson PX-8 Technical Manual page 172

REV.-A
*
CK input: I/O port 03 (H) read by RAM disk unit - FF output read.
*
R input : PX-S reset or I/O port 01
(H)
write by RAM disk unit - program reset.
3. Data and command registers
Two S-bit registers are provided for input and output which serve as buffers (temporary data
storage) used during data transfers between the RAM disk unit and Main Frame. Their input/
output or read/write is controlled via an address assigned to them. The data is directed on the
data bus from/to the registers under a directional control by the data bus control feature provid-
ed by a tri-state buffer IC "SA". Fig. 3-30 shows the data transfer directions and the direction
control circuit.
CPU
~~.t. ~lD-RAM
3" 7 8 " 8
0 ' 2 3 4 5 6 7 6
ocp!.-
H371. (B)
(KilL
° ' 2 3 4 5 7 6
OO(H) (DATA) IN'I
9
1
WRITE
t',
17
2 5 6 2 6\q
a
I
1
I.
678
I
03 READ
H
3fJ"
98)
~f(i
o
1 1 4 5 6 7 8
e"1--
3
I.
,3
~8
1-'>-·--81 (COMMAND)
or
80 (DATA) WRITE
READ
)
WRITE
(
1 ,.
II
~
.I
RM3
____ I
J_
2 3 " 5 6 7 8 8
80(H) (DATA)
19A
' M ,' O
READ
=t+t+tt~========~~~~~==========================~=it9
8 E
8a~lwe~llhr~Hrl~
./.A 7
~ ~:""'I.LlI.~!H!'I.~~
~
A5
~
B5
" 3 BJ
1Y/WP'Hl ....
==:~=======~====================1t~(8AI~; ~~
DI~ 3.JK x8
READ------------------------------------------------------------~~ 17~18~19~~~~~
o
2(2
J
~\
6 7
Fig. 3-36 Data Transfer Directions and Control
ICs "S8" and "98" contain eight tri-state D-type FFs each. The FFs read and latch data from either
data bus as arrowed when the "CK" signal rises. When the
"oc"
signal goes low, the latched data
becomes available onto the data bus from the output
(Q)
terminals.
• IC "98" is the Input register. It latches a data directed from Main Frame via address S1
(H).
This
data is then transferred to the RAM disk CPU when it reads its I/O port 03 (H).
• IC "S8" is the Output register. It latches a data when the RAM disk CPU writes to its I/O port
00
(H).
Then, the latched data is sent over the data bus to Main Frame when it reads its I/O port
SO (H) ..
• The tri-state buffer register "SA" is controlled by the DIR input signal. When this signal is high,
the "bufferred" data is directed from the RAM disk unit to Main Frame. When the signal is low,
the data transfer direction is reversed.
3-26