Gate Array Gah40D - Epson PX-8 Technical Manual

REV.-A
7.4 Gate Array GAH40D
GAH40D is the gate array for D-RAM control. It controls memory access and memory refresh. It
also incorporates a clock frequency divisor which divides 9.8 MHz input to 4.9 MHz, 2.45 MHz, 32
KHz and 1 KHz of clock frequency. Fig. 7 -4 shows an internal block of diagram of the GAH40D.
...
~
...
BANK
...
IPL ROM
AB15
CONTROL
BANKO
...
RO
I
4
n
RAS
CAS
~
WE
Generating
O-RAM
MREQ
.... circuit
BK2
9.8MHz , Frequency divisor
1/2
1 1/4 11/9800
II
4.9M 2.45M 1 K OW OCAS
Fig. 7-4
The BANK 0/1 signal is provided from the gate array GAH40M. The main CPU sends this signal
by writing bit 0 to I/O address 00. (0: bank 0, 1: bank 1)
BK2 signal is provided from the option unit.
7-12