Epson PX-8 Technical Manual page 177

REV.-A
3.2.10 Clock Signals
Two clock signals of 9.8 MHz and 32.768 kHz
are generated in the RAM disk unit. 9.8 MHz
clock signal is divided in gate array GAH40D to
2.45 MHz and fed to the CPU. The 32.768 kHz
clock signal is also divided in the gate array and
used as the DRAM refreshing signal. Fig. 3-42
shows the clock signal oscillator circuits.
3.2.11 DRAM Banks
The DRAM circuit is organized as
shown in fig. 3-43 and controlled
by gate array GAH40D.
It is read/written and refreshed
(also while Main Frame power is
off) in the same way as Main Frame
RAM. This unit has two DRAM
banks of 64 K bytes each and can
provide a capacity of 64 K or 1 28 K
bytes. Two signals DCAS and DW,
which determine a refresh mode
while power is off, are applied from
Main Frame.
• IC "9C" is provided to ensure the
address output that can drive
128 K bytes of RAM.
G
A
H
4
o
D
II K 1"-5,,------,
TES T 52
9&"1 F-"9'---+-----+--<
T
lOP
TIO P
mCB
rtr
C5
7, H CO,
Fig. 3-42
BIT 7
BIT6
BIT 5
I
BIT4
BIT 3
BIT 2
BIT 1
BITO
Bank 0/1 Bank 2
64KB 64KB
Fig. 3-43 DRAM Circuit Organization
3-31