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REV.-A
,uPD7001
1. location: MAPLE Board, 1 D
2. Pin Assignments
EOC
Dl
51
5CK
50
C5
Clo
ClI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD (+5V)
VREF
ANGND
A3
A2
Al
Ao
vss
Table 7-11 ,uPD 7001 Pin Assignments
Pin No.
Signal Name
In/Out
Function
-
1
End of Conversion
Open drain-
High impedance while CS is low, returns
- -
(EOC)
output
low when A - D conversion ends.
2
Data latch (Dl)
In
latches the multiplexer address in the shift
register at its falling edge.
3
Serial Input (SI)
In
Terminal which provides multiplexer address
to be read to the shift register.
The serial input data is read at the rising edge
of the SCK signal.
- -
4
Serial Clock (SCK)
In
Controls the shift operation of the 9-bit inter-
face shift register.
-
6
Chip Select (CS)
In
Controls ,uPD7001's internal modes.
-
When CS is high: A-D conversion mode
When CS is low: Interface mode - Dl, SI,
- -
-
SCK, and SO, etc. have been strobed with CS.
-
All the terminals are disabled while CS is high.
7
Clock (Clo)
For connection of clock oscillation CR
8
Clock (Cl1)
For connection of clock oscillation CR
9
- (Vss)
Externally connect to the GND and analogue GND terminals
10
~
13
Analogue input
Analogue input pin
(Ao
~
A3)
14
Analogue (GND)
Ground pin for analogue input and reference input
15
Reference input
Used for full scale voltage setting.
(VREF)
Supply voltage of about +2.5V.
16
Power supply (Vcc)
Power supply pin (+5V)
7-35
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