Interrupt And Halt - Epson S1C60N03 Technical Manual

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

4.7 Interrupt and HALT

The S1C60N03 Series provides the following interrupt settings, each of which is maskable.
External interrupt: Input port interrupt (one)
Internal interrupt: Timer interrupt (one)
To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask
registers must be set to 1 (enable). When an interrupt occurs, the interrupt flag is automatically reset to 0
(DI) and interrupts after that are inhibited.
Figure 4.7.1 shows the configuration of the interrupt circuit.
K00
EIK00
K01
EIK01
K02
EIK02
K03
EIK03
IT2
EIT2
IT16
EIT16
IT32
EIT32
HALT mode
When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The
oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits
the HALT mode and resumes operating.
30
IK0
Interrupt factor flag
Interrupt mask register
Fig. 4.7.1 Configuration of interrupt circuit
EPSON
Interrupt vector
(MSB)
:
Program counter of CPU
:
(three low-order bits)
(LSB)
INT
(Interrupt request)
S1C60N03 TECHNICAL MANUAL