Interrupt And Halt - Epson E0C6001 Technical Manual

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.9

Interrupt and HALT

The E0C6001 Series provide the following interrupt settings,
each of which is maskable.
External interrupt: Input interrupt (one)
Internal interrupt: Timer interrupt (one)
To enable interrupts, the interrupt flag must be set to 1 (EI)
and the necessary related interrupt mask registers must be
set to 1 (enable). When an interrupt occurs, the interrupt
flag is automatically reset to 0 (DI) and interrupts after that
are inhibited.
When a HALT instruction is input, the CPU operating clock
stops and the CPU enters the halt state. The CPU is reacti-
vated from the halt state when an interrupt request occurs.
Figure 4.9.1 shows the configuration of the interrupt circuit.
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