Omron 8025G Maintenance Manual page 98

THEORY OF OPERATION
4.4.B
CS3
"I
40 CHAR
DECODER
t-------------___ ..
SRIIIIH
~ S
SR CDUIIIT
CHARACTER
+
COUNTER
, 16
+
I
POS
TIME ...
H2O
. .
H40
..
CONTROL
H80
..
LOGIC
EOR
..
EDP
. .
f
:~':~:
BUS . .
I
E=C:.::..:::.::;:::..T-t . .
~1
READ!
I . . . . '
---~
- . . WIlITE -
81 ... LOGIC
BUFFER
CHARACTER
COUNTER
"5
ADDRESS
COUNTER
+ +
MEMORY SEAM
CONTROL
I
r
RDOl
POSITION
ADDRESS
GATE
ADDRESS
COUNTER
--.J
GATE
CNT80
t--
",A 0·2
MAO 13
RFAD DATA CHANNEL
..
RFF RN,'
..
Figure 4-18. Refresh control card block diagram.
Refresh Control Card
. SEen
. Block Diagram Analysis. As shown by the block diagram, in Figure 4-18,
the refresh
contro~
card consists of an address counter, a character counter and
the logic needed to control their operation. Also included are buffers to drive
the write· inputs of the refresh buffer card from the B Data Bus, and logic to gen
erate the MEMORY R/W control signal.
Whenever the refresh buffer takes a bus cycle, SR COUNT enables the two-
stage character counter for I count. 'The first stage counts from 0 to 15 and sup-
plies a carry output to the second stage. The second stage, preset to a count of
ten at the end of every character row, counts 5 of the first stage carry outputs
to generate CNT
BO.
The character counter thus counts the number of character
positions in a row.
Outputs from the character counter are decoded in the 40 character de-
coder to generate an output at the 40th character position. This output is used
only if the 40-character-per-row mode is enabled by
CS3.
In this mode the shift
register inhibit generator produces SRINH to disable the address gate during the
last half of the character row. SRINH has no active part in the refresh control
card operation in the standard BO-character-per-row mode.
At the end of each display page, the eight fixed positions in memory are
updated. They are addressed by the first stage of the character counter. UPDATE
presets this stage to a count of seven so that it can sequentially address the
eight fixed positions via MAO-2. Outputs from the counter are gated to the MA Dat:
Bus by SR COUNT and the
Q
output of the control flip-flop.