Omron 8025G Maintenance Manual page 93

THEORY OF OPERATION
SECI'ION 4
The XD RAM chips contain six special bytes, as follows:
• Keyboard indicators (illuninated keys); see Section 4.4.7
• Video status (video, cursor type); see Section 4.4.10
• Cursor position (row); see Section 4.4.9
Cursor position (column); see Section 4.4.9
• Page base (least significant bits); see Section 4.4.S
Page base (most significant bits); see Section 4.4.S
Table 4-4 gives RAM chip location as a function of memory address.
The video status address in memory also stores four bits of LED (light
emitting diode) data. Eight other LED bits are stored at memory address 37770 S '
All 12 of these bits are loaded into the LED latches during vertical retrace. The
LEDs themselves are located in the terminal keyboard, and each lights
up
whenever
a
tip'
is stored in the corresponding latch. (Note that only those LEDs that are
used for a particular configuration are installed in the keyboard).
Any time the refresh memory is addressed, a REF ADDR signal enables the
RM gate. As a result, RM data is placed on the A Data'Sus for use by either the CPU,
shift registers or DMA devices. With an SO-character-per-row display, the half-line
gate is always, open.
Data for an entire-character row (SO characters) is loaded into the re-
fresh shift register from the next row shift register at the end of every character
row. The refresh register functions as a la-cycle recirculating memory to supply
refresh data for the video display on CGO-7. When data has been transferred to the
refresh register, data for the following character row is read out of memory and
loaded into the next row register.
The·beep decoder decodes
I70,
IC eLK, and MA9-13 to provide a beep signal
for use on the cursor control card.
Circuit Description. Refer to schematic diagram 96-415-01 in Section S,
and to the timing diagram in Figure 4-17.
Whenever the refresh memory is addressed, REF ADDR is low at XD6-2 and -13.
If the CPU has not issued an 1/0, XD6-l will also be low. The resulting high output
at XD6-l2 enables the XC4, XB4 gates to couple RMC-7 to the A Data Bus.
The refresh shift regjster (XE2, XD2) is loaded from the next row shift
register (XE3, XD3) by signal EOR, which occurs during the 10th line scan for each
row of characters. During this line scan the data from the previous line of charac-
ters appears at the output of the refresh shift register while data for the next
row is moved in from the next row shi ft register. During the subsequent' 9 line scans,
the next row shift register is reloaded from refresh
me~ry
with data for the next
4-49