Omron 8025G Maintenance Manual page 100

THEORY OF OPERATION
SECTIO
and XC6 are loaded from 37775 S ' Load pulses are supplied via XA3-ll and -S, re-
spectively, by a decoding of the correct counts of the character counter (XB2) an(
XA4 pin 3 being high.
If the end of memory address (memory seam) is reached before the end of
the page, the seam is decoded in XBS-S and XB6-S. When the seam is decoded XB6-S
gets low, which resets XC3 and 4 to zero. If jumper El-E2 is not installed, XCS
is set to zero and the resulting address is 30,000 8 , If El-E2 is in place, XCS i!
set to binary 1000 and the resulting address is 34,000S' Note that XC6 had to be
set to binary 0011 (LLHH) to enable XB6.
When the end of memory address (37677 8 ) is reached it is decoded in
XBS-S and XB6-S, making XB6 pin 8 low, resetting XC3 and XC4 to address 30,000 8 ,
Note that, in a l2-line-per-page terminal, this causes the second half of the
screen to be loaded from nonexistent memory. That is, all nulls are loaded and
the bottom half of the screen is blank.
Note that page base data (addresses 37,774 S and 37,775 ) does not have
to be located at 30,OOOS but can be stored at any location in refreSh memory. Dur-
ing update at the end of the display page, the counter is loaded with page base
data via RMO-7. At the count of 10 in the character counter's (XB2) update cycle,
the level at pin 8 of XDI goes low and is OR-gated as a high input to XA3-l0.
Since bit A in the XB2 output is low at the count of 10, XA3-8 goes low to load
one byte of page base into XCS and XC6. At the count of II, bit A goes high. Con-
sequently, XA3-8 goes high and XA3-ll goes low to load the second byte of page
base into XC3 and XC4.
The remaining circuit on the refresh control card generates REF R/W.
This signal is CPU R/W or EXT WRT clocked with 01. EXT WRT is used by an external
device to write data into memory.
4.4.9 Cursor Control Card
The cursor tontrol card
the next character is to appear.
(click and beep) used in the 8025
the keyboard and the A Data Bus.
Block Diagram Analysis.
card is shown in Figure 4-19.
defines the position on the CRT display at which
It also generates the audio indicator signals
CRT Terminal and provides the interface between
A simplified block diagram of the cursor control
In addition to the cursor control circuitry, the cursor control card con-
tains the keyboard interface and repeat circuit, as well as the circuit used for
audio indications (click-beep).
A
DSO
(data strobe out) signals the keyboard interface that the keyboard
wants to send a character. When a POLL IN is received the interface selects itself
for the next data transfer to the CPU and gates the interface address onto the A
Data Bus. The CPU responds with an
100
signal that enables the gate to transfer
the keyboard data to the
A
Data Bus. IOD also generates OE (output enable). OE
signals the keyboard that the data was transferred, and the keyboard removes the
nso
to reset the interface control logic.
Removal of
nso
also triggers a one-shot that produces a O.S-second
pulse. If another data transfer has not occurred, the enable flip-flop is set to
enable a 15 Hz multi vibrator that, in turn, triggers a three-stage shift register.
4-S8