Omron 8025G Maintenance Manual page 89

THEORY OF OPERATION
SECTION 4
4.4.5
PROM Card
The PROM card serves as the program memory for the 8025 CRT Terminal.
Memory chips on this card contain all instructions needed by the CPU,to control
terminal operations.
Block Diagram Analysis. As shown by the simplified block diagram in
Figure 4-14, the PROM card has three major sections: an address sector gate, a
chip selector, and a memory that consists of sixteen 256-byte PROM chips. Full
addressing of the card is done on MAO-IS, with the state ~f MA14 and 15 always
held constant.
MA12-15
..
ADDRESS
ito
SECTOR
..
GATE
PROM
MEMORY A DATA BUS
CHIPS
..
1161
Ii!!A8-11
. .
CHIP
SELECTOR
t
MAO-7
Figure 4-14. Buffered PROM card block diagram.
The address sector gate defines the range of addresses to which the card
can respond. For addresses outside the range, the sector gate disables all the PROM
chips by inhibiting one of two enable inputs required by each chip. For addresses
within the defined range, MA12-IS will satisfy the gate, and it partially enables
all of the chips. -
Assuming the sector gate is satisfied, the chip selector supplies the
second enable input to the PROM chips specified on MAS-II. This second enable in-
put, plus addressing on MAO-7, defines the mem~ry location of the data to be read
out on the A Data Bus.
Circuit Description. Refer to Schematic diagram 96-434-XX in Section 8.
The maximum capacity
If fewer than 4,096 bytes are
unused chips are eliminated.
C of chips are eliminated.
of the PROM card is 4,096 bytes (32 chips) of memory.
needed for a particular version of the terminal, the
For example, if only 2,048 bytes are used, rows A and
Four inverters (XFS pins,2, 8, 10 and 12), header XF6 and NAND gate XE6-8
form
the address sector gate circuit. The four most significant address bits
(MA12-IS) are wired on the header to define the address sector for the card. For
the card shown, jumpers E2-E1S, F.4-E13, ES-E12 and E7-E10 are in place to define
address sector
°
(addresses 08 to 3777 8 ),
The six highest bits of address are transferred during CPU state T2. Ad-
dresses are changing during T1 and T2, but are stable throughout T3.
~~I4
and 15
are hard"wired at a high level for this system.
4-45