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GENERAL INFORMATION
SECTION 1
REF R/W:
Refresh read/write; controls writing of data into Refresh Memory.
RESYNC:
CPU SYNC c·utput reclocked with
9J2.
RMO-7:
Output data bits from Refresh Memory.
RPT:
Repeat; signal to Keyboard telling it to repeat last character
transferred as long as the
key
is depressed.
RS CLK:
Clock used to generate timing reference for I/O data transfer
RS 232 cards,
RSTO-2:
Restart command bits; inserts program address into CPU.
SET LDFF:
Set load flip-flop; output of load
flip-flop~loads
video parallel-
to-serial converter.
SPKR:
Speaker; produces audible energy generated by BEEP oscillator
circuit.
SR COUNT:
Indicates refresh logic has control of memory bus.
SRINH:
Shift register inhibit; controls loading of display shift
register in half line mode.
STAT:
Status; decode of CPU I/O command (INP2).
SYNC:
Output of CPU; indicates CPU is on second half of a timing state.
T2 SYNC:
Second hilI of CPU T2 timing state.
T3':
Early T3 timing state; synced with IC CLK.
T3 SYNC:
Second half of CPU T3 timing state.
UA ClK:
Universal asynchronous clock; clocks transmitter-receiver on
RS 232 Interface card.
UNO
BlNK:
Undelayed blanking signal.
UPDATE:
pulse occuring at frame rate controlling updating of hardware
parameter from
6
fixed locations in memory.
VI, V2, V4:
Timing signal;
defines scanning lines one through eight
(character row lines are numbered
0
through
9) .
V8:
VlO:
.
Timing signal; defines scan line nine
(8)
by itself, defines
scan line ten
(9)
in conjunction with VI.
Differentjatcs between even and odd vertical rows.
1-15
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