Omron 8025G Maintenance Manual page 84

THEORY OF OPERATION
SECTION 4
RC is inverted by XD6-14 to
rue.
RC blanks the CRT during vertical retrace,
which occurs during the last two character rows in a frame. It is also divided by
12 in XD6 to produce the RATE (rate clock) at 5 Hz.
Vertical sync (V SYNC) signals are derived by gating V4, V8, RC and VIO
through XEl-'IO and -13 and XE2 to the two-character delay, XE3. V SYNC, with a
350 usec pulse width, occurs at a 60 Hz rate.
Composite sync (COMP SYNC) is obtained by OR-gating the horizontal sync
and vertical equalization pulses in XE2-11 to the 2D input of XE3. Vertical com-
ponents are gated through to XDI-8 during V DRIVE when V4 and H SYNC at XC3-8 are
high. Thus, during the display position of the field of COMP SYNC pulses are 8.04
usee long, occuring once every horizont.al line. During the vertical sync period
there are four 54 usec pulses at the horizontal frequency. COMP SYNC is also
applied to XE3.
Composite blanking (COMP BLNK) is the OR-gated combination of H BLNK,
vertical blanking (RC), and 10th through 12th lines of ea~h character row (SO Hz
version only). The 10th through 12th line input to OR gate XD3 (pin 4) is low when
VI and V2 are high at XEl-S and -6. Composite blanking is applied to the two-
character delay (XE3) and also to an inverter (XF3-l2) to supply an undelayed hlanking
(UND
BLNK) signal.
The remaining signals generated on the Timing Control Card are cursor
line (CURS LINE), end of page (EOP), and set load flip-flop (SET LDFF).
Cursor line is produced by XDI (pin 6) whenever VI and V2 are low at
pins
5
and 6 of XEl and V8 is high. EOP is generated by decoding RC, VIO, and EOR
in XF2-6. A 63.6 usec output pulse, with a 60 Hz rate, appears at XF3-8 at the end
of every 24 character rows. SET LDFF is the NAND combination of HI and H8 at XC6-6.
This signal has a pulse width of 67 nsec and an H8 repetition rate (1.497
MHz).
4.4.4 Processor Card
The processor card controls nearly all terminal operations. It polls cards
on the A Data Bus to determine whether a card is ready to transfer data in either
direction. When a card is ready, the processor--working with the terminal memory--
interprets and processes the data and enables the transfer.
Block Diagram Analysis.
A
simplified block diagram of the processor card
is provided in Figure 4-12. The processor card centers around an IC central processor
unit (CPU) designed to work with an external memory. Data enters and leaves the
CPU on an internal time-multiplexed data bus. The CPU has eight timing states,
labeled and defined as follows:
TI: Time used to load least significant eight bits
o~
,d-
dress into external memory and increment CPU program
counter.
T2: Time used to load most significant six bits of address
and two control bits into external memory; also to in-
crement CPU program counter with a carry from Tl.
4-39