Omron 8025G Maintenance Manual page 116

THEORY OF OPERATION
SECTION 4
Receipt of a POLL at XG6-4 and -10 enables the two gates. If the receiver
is not ready, XG5-5 is'low to inhibit XG6 at pin 5, and XGS-6 is high. As a result,
the POLL is gated to XG6-13 and -1. If the transmitter is not ready, XG5-3 is low
to inhibit XG6 at pin 12, and XGS-2 is high. Thus, the POLL output at XG6-3 is tran~
ferred to the next card·installed. XG6-6 and -11 are low when the card is not ready
to transfer data. With these two low levels at XCS-4, and -5, XCS-6 is low to in-
hibit
~he AfiiIT
through ADB4 gates (XD2-11, -6, -3 and -S) and, consequently, the car(
address is not placed on the A Data Bus. That is, ADBl-4 is high. The low level at
XG6-ll is also inverted by XD4-l2 to make ADBO high.
Assume the receiver is ready. In this
c~se
the DR output (pin 19) of XG3
is high to indicate that received data is available. This high level at XGS-S causes
CGS-S to change state (go high) on the next IC CLK pulse (XE6-8) .. With XGS-S high,
gate XG6-6 is enabled and gate XG6-S is inhibited by the low level at XGS-6. The
latter prevents POLL propagation while the former applies a high level when POLL ar-
rives, to XCS-lO, XCS-S, and XF6-l.
The high level at XCS-lO is gated to pins 4, 2, and 12 of the error gates
(XG1) to enable them. The address gates (XD2) are enabled at pins 12, 5, 2, and 10
by the high XC5-5 and 6. Thus, the card address (as determined by the strapping on
XA2) is gated to ADBl-4. (NOTE: SWl-4 are not installed in this terminal.) When
XC5-5 is high, XG6-ll is low, since the transmitter flip-flop is low at XG5-3. The
low level at XG6-ll, inverted at XD4-l2, makes ADBO high to indicate that the card
is in the receive mode.
The high level at XF6-l causes XF6-3 to go high on the next IC CLK pulse
at XF6-l2, enabling the XF5-3 gate. Without an 100, the low level at XF5-3 inhi-
bits the received data gates (XF1, XE2) at pins 2, 4, 12, and 10.
. When the
CP~
sends an 100, XF5-3 goes high to enable the received data
gates and, consequently, the character in XG3 is placed on the A Data Bus. The high
level at
XF5~3
is also clocked with IC CLK, and the resulting low level at XF4-3 is
applied to the DRR input (pin IS) of XG3 to reset its DR output to a low level. When
DR goes low it deselects the card on the next IC CLK by resetting the XGS and XF6
receiver ready flip-flops (XGS-S and XF6-3 lOW). The change in state of XG5 and XF6
performs three functions: (1) it permits' transfer of the next POLL to XG6-l3 and -1;
(2) it disables the received data gates; and (3) it causes XF5-3 to go low, XF4-l
to go high, and XCl-S to go low to load the error latch (XG2). Note that a RCVR OFF
signal (XE5-l3 low) will also set XGS and XF6 to the not ready state (XGS-6 high).
The other section of the XG5-XF6 logic controls transmitter loading. Oper-
ation is essentially the same as that described for the'receiver control flip-flops.
In this case, however, the transmitter ready state is defined
by:
(1) a signal from
the transmitter indicating that the transmitter register is available for loading
(THRE, pin 22, of XG3 is high); (2) the presence of a clear to send (CB) signal
(XB5-10 high); (3) a high level at XES-12 (transmitter on); and (4) the absence of
BREAK.
If CB and THRE are high at XC3-l2 and -11, respectively, XG5-3 will set
low (transmitter off). If either XE5-l2 or BREAK is low at XF5-9 and -10 respective-
ly, XGS-3 will be cleared, at pin 10, to a low level. If XE5-12 and BREAK are high,
along with a low CB and THRL at XC3-l0 and -11, XGS-l is set high on the next IC CLK
to enable the XG6-l1 Rate. The next POLL at XG6-l3 produces a high level at XF6-8.
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