Omron 8025G Maintenance Manual page 90

THEORY OF OPERATION
SECfION 4
For any address between
Os
and 3777 S ' MA12 and 13 are low. Inversion
through XF6 places high inputs on pins 11 and 12 of gate XE6. MA14 and 15 are
also high at the input to XE6-S with
170
also high, XE6-8 applies a low partial en-
able input to C52 (pin 14) of each PROM chip. Any change in the inputs to the ad-
dress sector gate will cause the output of XE6-8 to go high to inhibit all chips.
Inputs MAS-II select the PROM chips to be addressed. These inputs are
converted in two BCD-to-decimal decoders (XE4 and XES), and each output of the
decoder is applied to the
as
inputs (pin 13) of two PROM chips (e.g., the output
at XES-l is applied to PROM chips XBI and XDl). A low input at
as
selects the two
chips for reading. The lower four and higher four data bits are stored in the XB
and XD series PROM chips, respectively.
Eight bits of address (MAO-7) plus a low input at both
as
and C5 2 allow
the data stored in the two chips to be read onto the A Data Bus.
Table 4-3 gives PROM chip location as a function of memory address.
Table 4-3. PROM chip location
VB.
memory address.
PROM CHIP COORDINATES
MOST LEAST
MEMORY ADDRESS
SIGNIFICANT
SIGNIFICANT
BITS
BITS
(in octal)
.
-
XD1 XB1 00000 - 00377
XD2 XB2
00400 - 00777
XD3 XB3
01000 - 01377
XD4 XB4 01400 - 01777
XDS
XBS 02000 - 02377
XD6
XB6 02400 - 02777
XD7
XB7 03000 - 03377
XDB XBB 03400 - 03777
XCI XE1
04000 - 04377
XC2 XE2
04400 - 04777
4-46