Omron 8025G Maintenance Manual page 117

THEORY OF OPERATION
SECTION 4
The high level at XF6-8 does three things. It (1) enables the address
gates (XD2-12, -5, -2, -10) via the XC5-6 gate; (2) places a low level on ADBO via
XD4-l2, -13 and XG4-l0,
-11
to indicate transmit mode; and
(3)
causes XF6-S to be
set high on the next IC CLK, which enables the XF4-8 gate when IOD occurs.
The resulting low level at XF4-8 applied to the THRL input (pin
23)
of
XG3, loads the character on MAO-7 into the transmitter holding register. When XF4-S
subsequently makes the transition from low to high, it transfers the character to
the transmitter register if the latter is not in the process of transmitting a char-
acter. If transmission is still in process, the ~ransfer from the holding register
is delayed until transmission has been completed.
The status signal reads the state of the interface card, sets the state of
the receiver-transmitter, and sets output control signals.
When the CPU is ready for a read status transfer, it sends a STAT command
to the interface card. STAT is sent only after the CPU is prepared to send the card
address.
Four address bits on MAl-4 are applied to XD3-l3, -8, -2 and -5, respective-
ly. The card address, determined by the strapping on XA2, is applied to four exclu-
ive NOR gates (XD3-12, -9, -1 and -6) that function as a comparator. If the address
sent by the CPU matches the card address, the comparator puts out a high level to
enable gate XE6 at pin
1.
With XE6 enabled, the card can accept STAT at XE6-2.
STAT enables four of the status gates (XEI) at pins 10, 13, 2, and 5, and
the fifth status gate (XGl) at pin 10. This places five status bits on the A Data
Bus. Received line signal detector (CF) is gated to ADBO at XEl-S; ADBI and
2
are
not used. The ihput on XEl-4, derived from CB (clear to send), THRE, and TRE, is
gated to ADB3 to report transmission status. THRE indicates if XG3 can be loaded,
and TRE indicates if XG3 is transmitting a character. If XEl-4 is low, the trans-
mitter is not availabie. Ring indicator (CE) is gated to ADBO at XGl-S.
STAT is also OR-gated through XCS-B, and the resulting high level at XC5-8
enables the three error gates (XG1-ll, 73 and -6); PE (parity error), gated to ADB5,
indicates that the last character received by XG3 contained a parity error. FE
(framing error) is gated to
ADB6
to indicate a missing stop bit in a received char-
acter. (This event will occur if there is noise on the line or a BREAK command is
received.) OE (overrun error), gated to ADB7, occurs when the CPU did not transfer
a received character before a new character was received.
The output on XE6-3 (STAT AND-gated with the address comparator output) en-
ables XF5 at pin 4. STAT is also clocked by IC CLK to produce a high output at
XE6-11. This output is gated to XF5-6 to enable XF4 at pins 12 and 4. Thus, MAS
and 7 are gated to XE4-14 and -12, respectively. MAO and MA6 are applied to pins }S
and 13, respectively, of XE4. XE4, the command decoder, decodes the states of ~~O,
S, 6, and 7 to set the RS-232 interface status. The inputs and corresponding out-
put states for XE4 are given in Table 4-10.
In summary, the RS-232 Interface Card responds to a POLL with its address,
error status, and operating mode. The card responds to a read status command (STAT
plus MAO high .or low and MAS-7 low) with error, transmitter availability, ring indi-
cator, and received line signal detector status. For a set status command (STAT
4-75