Hyundai H-HT5115-N Service Manual page 97

ESMT
3. CAS Interrupt (I)
1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 )
C L K
C M D
R D
A D D
A
D Q ( CL 2 )
DQ ( C L 3 )
t
C C D
* N o t e 2
2 ) W r i t e i n t e r r u p t e d b y W r i t e ( B L = 2 )
CL K
C M D W R
t
C C D * N o t e 2
A
A D D
D Q
DA 0
t
C D L
* N o t e 3
*Note : 1. By "interrupt" is meant to stop burst read/write by external before the end of burst.
By " CAS interrupt ", to stop burst read/write by CAS access; read and write.
2. t : CAS to CAS delay. (=1CLK)
CCD
3. t : Last data in to new column address delay. (=1CLK)
CDL
Elite Semiconductor Memory Technology Inc.
* N o t e 1
RD
B
Q B 1
Q A 0 Q B 0
Q A 0 Q B 0
W R
B
D B 0 DB 1
Q B 2 Q B 3
Q B 1
Q B 2 Q B 3
3 ) W r i t e i n t e r r u p t e d b y R e a d ( B L = 2 )
D Q ( CL 2 )
DQ ( C L 3 )
M12L64164A
W R RD
t
C C D * N o t e 2
A
B
D A 0
DB 0
D A 0
D B 0
t
C D L
* N o t e 3
Publication Date: May 2008
Revision: 3.3
D B 1
D B 1
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